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| TECHNICAL DATA DTMF RECEIVER High-Performance Silicon-Gate CMOS The IL9270N/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dialtone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface. * Complete receiver in an 18-pin package. * Excellent performance. * CMOS, single 5 volt operation. * Minimum board area. * Central office quality. * Low power consumption. IL9270 D SUFFIX SOIC ORDERING INFORMATION IL9270N/D TA = -10 to 70 C LOGIC DIAGRAM PIN ASSIGNMENT * Connect to GND PIN 9 = GND PIN 18 = VCC PINS 5,6 = NO CONNECTION IL9270 PIN DESCRIPTIONS NAME ESt PIN 16 DESCRIPTION Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Gain Select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Internal Connection. Must be tied to GND. Non-Inverting Input Inverting Input Clock Input Clock Output Connections to the front-end differential amplifier. 3.579545 MHz crystal connected between these pins completes internal oscillator. GS IC IN+ INC1 C2 Q1-Q4 StD 3 5,6 1 2 7 8 11-14 15 3-state data outputs. When enabled by OE, provide the code corresponding to the last valid tone-pair received. Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Steering input/guard time output (bi-directional). A voltage greater than VTSt, detected at St causes the device to register the detected tone-pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 3-state output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up. Positive power supply, +5 V. Reference voltage output, nominally VCC /2. May be used to bias the inputs at mid-rail. Negative power supply, normally connected to 0 V. St/GT 17 OE VCC VREF GND 10 18 4 9 FUNCTIONAL DESCRIPTION The IL9270 monolithic DTMF receivers offer small size, low power consumption and high performance. The architecture consists of a bandsplit filter section, which separates the high and low tones of a receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. order for the low group. The band-widths of which correspond to the bands enclosing the low-group and high-group tones (see Figure 1). The filter section also incorporates notches at 350 Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second order switched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted lowlevel signals and noise; the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Filter Section Separation of the low-group and high-group tones is achieved byapplying the dual-tone signal to the inputs of two filters - a sixth order for the high group and an eight IL9270 Decoder Section Guard Time Adjustment The decoder uses digital counting techniques to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals, such as voice, while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to "talk-off" and tolerance to the presence of interfering signals ("third tones") and noise. When the detector recognizes the simultaneous presence of two valid tones (referred to as "signal condition" in some industry specifications), it raises the "early steering" flag (ESt). Any subsequent loss of signal-condition will cause Est to fall. In many situations not requiring independent selection of receive and pause, the simple steering circuit of Figure 2 is applicable. Component values are chosen according to the following formula: tREC = tDP + tGTP tID = tDA + tGTA The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 F is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40 ms would be 300 k. Different steering arrangements may be esed to select independently the guard-times for tone-present (tGTP) and tone-absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and inter-digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. Design information for guard-time adjustment is show in Figure 4. Steering Circuit Before registration of a decoded tone-pair, the receiver checks for a valid signal duration (referred to as "character-recognition-condition"). This check is performed by an external RC time-constant driven by ESt. A logic high on ESt causes VC (see Figure 2) to rise as the capacitor discharges. Provided signal-condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone-pair, latching its corresponding 4-bit code (see Figure 3) into the output latch. At this point, the GT output is activated and drives VC to VCC. GT continues to drive high as long as ESt remains high. Finally after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling that a received tone-pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the 3-state control input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Input Configuration The input arrangement of the IN9270 provides a differential-input operational amplifier as well as a bias source (VREF) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 5 with the op-amp connected for unity gain and VREF biasing the input at 1/2VCC. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. IL9270 MAXIMUM RATINGS* Symbol VCC VIN IIN PD Tstg * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC InputCurrent, per Pin Power Dissipation in Still Air, Storage Temperature Plastic DIP ** Value -0.3 to +6.0 -0.3 to VCC +0.3 10 500 -65 to +150 Unit V V mA mW C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating: -10 mW/C from 65C to 70C. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN TA PO tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature Power Consumption ( f = 3.579 MHz, VCC = 5 V) Input Rise and Fall Time Min 4.75 1.5 -10 0 Max 5.25 3.5 +70 45 110 Unit V V C mW ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. IL9270 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, VCC = 5 V 5%, TA = -10 to +70C) Guaranteed Limits Symbol VIH VIL VOH VOL IIN ISO IOL IOH ICC Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Pull Up (Source) Current Minimum Output-Low (Sink) Current Minimum Output-High (Source) Current Maximum Quiescent Supply Current (per Package) Steering Threshold Voltage Input Impedance (Signal Inputs 1,2) Output Voltage Output Resistance Maximum Three-State Leakage current Output in HighImpedance State VIN =VIL VOUT=VCC or GND @ 1 KHz No Load Test Conditions VOUT =5 V VOUT =5 V No Load No Load VIN=VCC or GND OE = 0 V VOUT =0.4 V VOUT =4.6 V VIN =VCC 0.8 0.35 11 4.97 0.05 0.1 24 Min 3.6 1.4 Typ Max Unit V V V V A A mA mA mA VTSt RIN VREF ROR IOZ 2.2 8 2.4 10 2.5 V M 2.8 0.1 V k A IL9270 OPERATING CHARACTERISTICS Gain Setting Amplifier Symbol IN RIN VOS PSRR CMRR AVOL fC VO CL RL: VCM Parameter Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection DC Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Tolerable Resistive Load (GS) Tolerable Resistive Load (GS) Common Mode Range No Load RL 100 K to GND 1 KHz -3.0 V < VIN < 3.0 V Test Conditions GND< VIN < VCC Typ 100 10 25 60 60 65 1.5 4.5 100 50 3.0 Unit nA M mV dB dB dB MHz VPP pF K VPP AC ELECTRICAL CHARACTERISTICS (All Voltages referenced to GND. VCC = 5.0 V, GND = 0 V, TA = -10 to +70C, FCLK = 3.579545 Mhz, using test circuit of Figure 5) Parameter SIGNAL CONDITION Valid Input Signal Level (each tone of composite signal) NON-ACCEPT LEVEL Freq. Deviation Accept Limit Freq. Deviation Reject Limit Third Tone Tolerance Dial Tone Tolerance 3.5% -2.5 +18 1.5% 2 Hz Nom. Nom. dB dB 2,3,5,9 2,3,5 2,3,4,5,7,9,10 2,3,4,5,8,9,10 MAX +1 883 MIN -29 27.5 dBm m VRMS dBm m VRMS 1,2,3,5,6,9 1,2,3,5,6,9 1,2,3,5,6,9 Guaranteed Limits Min Typ Max Unit Notes IL9270 TIMING REQUIREMENTS (All Voltages referenced to GND. VCC = 5.0 V, GND = 0 V, TA = -10 to +70C, FCLK = 3.579545 Mhz, using test circuit of Figure 5) Symbol Parameter Guaranteed Limits Min tDP tDA tREC tREC tID tDO tPQ tPSED tQSED tPTE tPTD fCLK CLO Notes: Tone Present Detection Time (Figure 7) Tone Absent Detection Time (Figure 7) Maximum Tone Detection Accept (Figure 7) Minimum Tone Detection Reject (Figure 7) Maximum Interdigit Pause Accept (Figure 7) Minimum Interdigit Pause Reject (Figure 7) Maximum Propagation Delay (St to Q) (Figure 7) Maximum Propagation Delay (St to StD) (Figure 7) Maximum Output Data Set Up (Q to StD) (Figure 7) Maximum Propagation Delay (OE to Q) (Figure 7) Clock Output (C2) ENABLE DISABLE 3.5759 Capacitive Load 20 11 16 5 75 460 3.581 30 20 40 5 0.5 Max 18 10 40 Unit ms ms ms ms ms ms s s s ns ns MHz pF RL= 10 K CL= 50 pF Refer to "Guard Time Adjustment" OE = VCC Notes Refer to Fig. 7 (User Adjustable) Crystal/Clock Frequency 1. dBm = decibels above or below a reference power of 1 mW into a 600 load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40 ms, Tone pause = 40 ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amlitude. 6. Tone pair is deviated by 1.5% 2 Hz. 7. Bandwidth limited (3 KHz) Gaussian Noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) 2%. 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest level frequency component in DTMF signal. Figure 1. Typical Filter Characteristic IL9270 tGTA = (RC) ln () VCC VTST tGTA = (RC) ln ( VCC VCC - VTST ) Figure 2. Basic Steering Circuit FLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 KEY 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY OE H H H H H H H H H H H H H H H H L Q4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z Q3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z Q2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z "L = Logic Low, H = Logic High, Z = High Impedance" Figure 3. Logic Table IL9270 tGTP= (RPC) ln ( ( VCC VCC - VTST VCC VTST ) tGTA = (R1 C) ln R1 R2 RP = R1 + R2 ) a) Descreasing tGTP ( tGTP < tGTA ) tGTP= (R1C) ln ( ( VCC VCC - VTST VCC VTST ) tGTA = (RPC) ln R1 R2 RP = R1 + R2 ) b) Descreasing tGTA ( tGTP > tGTA ) Figure 4.Guard Time Adjustment Figure 5. Single Ended Input Configuration IL9270 Figure 6. Differential Input Configuration TIMING DIAGRAM A. B. C. D. E. F. G. Short tone bursts: detected. Tone duration is invalid. Tone #n is detected. Tone duration is valid. Decoded to outputs. End of tone #n is detected and validated. 3 State outputs disabled (high impedance). Tone #n+1 detected. Tone duration is valid. Decoded to outputs. Tristate outputs are enabled. Acceptable drop out of tone #n+1 does not register at outputs. End of tone #n+1 is detected and validated. IL9270 EXPANDED LOGIC DIAGRAM IL9270 N SUFFIX PLASTIC DIP (MS - 001AC) A Dimension, mm 18 10 B 1 9 Symbol A B C MIN 22.35 6.1 MAX 23.37 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLANE G H H J N G D 0.25 (0.010) M T K M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AD) A 18 10 Dimension, mm Symbol MIN 10.1 7.4 2.35 0.33 0.4 1.27 MAX 10.5 7.6 2.65 0.51 1.27 H B A B 1 G 9 C R x 45 C D F -TD 0.25 (0.010) M T C M K SEATING PLANE J F M G H J K M P R 0 0.1 0.23 10 0.25 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 8 0.3 0.32 10.65 0.75 |
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